1. Field of the Invention
The present disclosure relates to programming in non-volatile memory.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electronically Programmable Read Only Memory (EPROM) are among the most popular non-volatile semiconductor memories.
EEPROM and EPROM memories utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. The minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming a flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in the programmed state.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state). For example, FIG. 1 shows a graph depicting two threshold voltage distributions. The x axis plots threshold voltage and the y axis plots the number of memory cells. The threshold voltages in distribution 2 are less than zero volts. In one embodiment, threshold voltage distribution 2 corresponds to erased memory cells that store data “1.” The threshold voltages in distribution 4 are greater than zero volts. In one embodiment, threshold voltage distribution 4 corresponds to programmed memory cells that store data “0.”
A multi-state flash memory cell is implemented by identifying multiple, distinct allowed threshold voltage ranges separated by forbidden voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits. FIG. 2 illustrates threshold voltage distributions for memory cells storing two bits of data through the use of four data states. In one embodiment, threshold voltage distribution 2 represents memory cells that are in the erased state (e.g., storing “11”), having negative threshold voltage levels. Threshold voltage distribution 10 represents memory cells that store data “10,” having positive threshold voltage levels. Threshold voltage distribution 12 represents memory cells storing data “00.” Threshold voltage distribution 14 represents memory cells that are storing “01.” In some implementations (as exemplified above), these data values (e.g. logical states) are assigned to the threshold ranges using a gray code assignment so that if the threshold voltage of a floating gate erroneously shifts to its neighboring physical state, only one logical bit will be affected. In other embodiments, each of the distributions can correspond to different data states than described above. The specific relationship between the data programmed into the memory cell and the threshold voltage ranges of the cell depends upon the data encoding scheme adopted for the memory cells. For example, U.S. Pat. No. 6,222,762 and U.S. patent application Ser. No. 10/461,244, “Tracking Cells For A Memory System,” filed on Jun. 13, 2003, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells. Additionally, embodiments in accordance with the present disclosure are applicable to memory cells that store more than two bits of data.
Threshold voltage distributions 2 and 4 show the erased and programmed voltage-distributions when no verify operations are used. These distributions can be obtained by programming or erasing the memory cells with one single programming or erase pulse. Depending on the memory array size and the variations in the production process, threshold voltage distribution 4 will have a certain width, known as the natural Vth width.
As can be seen from FIG. 2, distributions 10, 12, and 14 (corresponding to programming a multi-state device) need to be much narrower than the natural Vth width of distribution 4. To achieve narrower threshold voltage distributions, a process that uses multiple programming pulses and verify operations, such as that described by FIGS. 3A, 3B, and 3C, can be used.
FIG. 3A depicts a programming voltage signal Vpgm that is applied to the control gate as a series of pulses. The magnitude of the pulse is increased with each successive pulse by a pre-determined step size (e.g., 0.2V-0.4V), depicted in FIG. 3A as ΔVpgm. In the periods between the pulses, verify operations are carried out. As the number of programmable states increases, the number of verify operations increases and more time is needed. One means for reducing the time-burden is a more efficient verification process, such as the process that is disclosed in U.S. patent application Ser. No. 10/314,055 entitled, “Smart Verify For Multi-State Memories,” filed Dec. 5, 2002, incorporated herein by reference in its entirety. In reality, the pulses of FIG. 3A are separated from each other by a time period during which verification is performed. However, to make FIG. 3 more readable, the time period for verification is omitted from the drawing.
FIG. 3B depicts the voltage signal applied to a bit line for the associated memory cell being programmed. FIG. 3C depicts the threshold voltage of the memory cell being programmed. Note that the graph in FIG. 3C is smoothed out to make it easier to read. After each programming pulse, a verify operation is carried out (not shown.) During the verify operation, the threshold voltage of the memory cell to be programmed is checked. If the threshold voltage of the memory cell is larger than the target value (e.g., Vverify), then programming for that memory cell is inhibited in the next cycle by raising the bit line voltage from 0 v to Vinhibit (e.g., at time t4).
As with other electronic devices, there is a consumer demand for memory devices to program as fast as possible. For example, the user of a digital camera that stores images on a flash memory card does not want to wait between pictures for an unnecessary long period of time. In addition to programming with reasonable speed, to achieve proper data storage for a multi-state memory cell, the multiple ranges of threshold voltages of the multi-state memory cells should be separated from each other by sufficient margin so that the level of the memory cell can be programmed and read in an unambiguous manner. A tight threshold voltage distribution is recommended. To achieve a tight threshold voltage distribution, small program steps have typically been used, thereby programming the threshold voltage of the cells more slowly. The tighter the desired threshold voltage distribution the smaller the steps and the slower the programming process.
One solution for achieving tight threshold voltage distributions, without unreasonably slowing down the programming process, includes using a two-phase programming process. The first phase, a coarse programming phase, includes an attempt to raise a threshold voltage in a faster manner while paying less attention to achieving a tight threshold voltage distribution. The second phase, a fine programming phase, attempts to raise the threshold voltage in a slower manner in order to reach the target threshold voltage, thus achieving a tighter threshold voltage distribution. One example of a coarse/fine programming methodology can be found in U.S. Pat. No. 6,643,188, incorporated herein by reference in its entirety.
FIGS. 4 and 5 provide more detail of one example of a coarse/fine programming methodology. FIGS. 4A and 5A depict the programming pulses Vpgm applied to the control gate. FIGS. 4B and 5B depict the bit line voltages for the memory cells being programmed. FIGS. 4C and 5C depict the threshold voltage of the memory cells being programmed. The example of FIGS. 4 and 5 depicts programming of memory cells to state A using two verify levels, indicated in the Figures as VvA1 and VvA2. The final target level is VvA2. When a threshold voltage of the memory cell has reached VvA2, the memory cell will be inhibited from further programming by applying an inhibit voltage to the bit line corresponding to that memory cell. For example, the bit line voltage can be raised to Vinhibit (See FIG. 4B and FIG. 5B). However, when a memory cell has reached a threshold voltage close to (but lower than) the target value VvA2, the threshold voltage shift of the memory cell during subsequent programming pulses is slowed down by applying a certain bias voltage to the bit line, typically on the order of 0.3V to 0.8V. Because the rate of threshold voltage shift is reduced during the next few programming pulses, the final threshold voltage distribution can be narrower than with the methods depicted in FIG. 3. To implement this method, a second verify level that is lower than that of VvA2 is used. This second verify level is depicted in FIGS. 4 and 5 as VvA1. When the threshold voltage of the memory cell is larger than VvA1, but still lower than VvA2, the threshold voltage shift to the memory cell will be reduced for subsequent programming pulses by applying a bit line bias Vs (FIG. 5B). Note that in this case, two verify operations are required for each state. One verify operation at the corresponding final verify level (e.g., VvA2) for each state to which the coarse/fine programming methodology is applied, and one verify operation at the corresponding second verify level (e.g., VvA1) for each state. This may increase the total time needed to program the memory cells. However, a larger ΔVpgm step size can be used to speed up the process.
FIGS. 4A, 4B, and 4C show the behavior of a memory cell whose threshold voltage moves past VvA1 and VvA2 in one programming pulse. For example, the threshold voltage is depicted in FIG. 4C to pass VvA1 and VvA2 in between t2 and t3. Thus, prior to t3, the memory cell is in the coarse phase. After t3, the memory cell is in the inhibit mode.
FIGS. 5A, 5B, and 5C depict a memory cell that enters both the coarse and fine programming phases. The threshold voltage of the memory cell crosses VvA1 in between time t2 and time t3. Prior to t3, the memory cell is in the coarse phase. After t3, the bit line voltage is raised to Vs to place the memory cell in the fine phase. In between t3 and t4, the threshold voltage of the memory cell crosses VvA2. Therefore, the memory cell is inhibited from further programming by raising the bit line voltage to Vinhibit.
Typically, in order to maintain reasonable programming times, coarse/fine programming algorithms are not applied to the highest memory state (the state corresponding to the largest positive threshold voltage range). The highest state, such as state C represented by distribution 14 in FIG. 2, does not need to be differentiated from a higher state. Typically, it is only necessary to program cells for this state above a minimum threshold level to differentiate from the next lowest state (e.g., state B represented by distribution 12). Thus, the distribution of these cells can occupy a wider threshold voltage range without adverse effects on device performance. However, some implementations will make use of coarse/fine programming techniques when programming the highest level state as well.